This invention relates to a hardware simulator for use in successively simulating logic operations of a plurality of gates included in a logic circuit.
Simulation of logic operations is effective in designing an assembly of gates for which logic operations are not yet decided and in assuring logic operations of a gate circuit which is already designed. As a rule, conventional simulation is carried out by the use of software and may be called software simulation.
An execution time of such software simulation tends to become long with an increase in an amount of test data signals necessary for the software simulation or with an increase in simulation clock signals. This results in software simulation for diagnosing a fault in a very big computer, such as a super computer being substantially impossible.
On the other hand, a hardware simulator is proposed as a dynamic gate array by Kenji Ohmori in the U.S. Pat. No. 4,541,071 assigned to the instant assignee. The hardware simulator is for use in simulating an overall operation carried out by a gate assembly comprising a plurality of gates. With this hardware simulator, each logic operation of the gates is simulated in consideration of those logic states of each gate which are determined by permutations. A great deal of logic states must be taken into account and stored in a permutation memory to be subjected to calculation. In addition, a gate memory must be included so as to the store results of calculation.
Memory capacities of the permutation memory and the gate memory must be exponentially increased with an increase of the logic states. This makes simulation of a large scale integrated circuit difficult.